The present invention relates to a semiconductor device; and, more particularly, to a phase locked loop (PLL) with a high-speed locking characteristic, which is capable of obtaining a fast locking time and a reduced jitter.
Generally, a phase locked loop (PLL) is widely used in a radio communication system, such as a frequency mixer, a carrier recovery circuit, a clock generator, a modulator/demodulator, and the like. In particular, systems employing a clock recovery circuit or a frequency hopping spread spectrum require a fast frequency/phase locking.
FIG. 1 is a block diagram showing a conventional PLL.
Referring to FIG. 1, a conventional PLL includes a phase/frequency detector (PFD) 10, a charge pump unit 20, a low-pass filter (LPF) 30, a voltage-controlled oscillator (VCO) 40 and a frequency divider 50.
The PFD 10 compares a phase/frequency of a reference signal SR having a predetermined frequency fR with that of a feedback signal SF having a feedback frequency fD, to thereby obtain a phase/frequency difference therebetween. Then, the PFD 10 produces a sequence of an up pulse UP and a down pulse DN according to the phase/frequency difference.
The charge pump unit 20 converts the phase/frequency difference into a positive pump current signal and a negative pump current signal in response to the up pulse UP and the down pulse DN, respectively.
The LPF 30 converts the positive pump current signal and the negative pump current signal into corresponding voltage signal.
The VCO 40 receives the voltage signal outputted from the LPF 30 and generates an output signal SOut having a predetermined oscillation frequency fouT that is varied with the inputted voltage signal.
The frequency divider 50 divides the oscillation frequency fOUT to output a divided oscillation frequency fD.
The PFD 10 again compares the reference signal SR with a feedback signal SF having the divided oscillation frequency fD as the feedback frequency. Then, the frequency/phase of the reference signal SR is synchronized with that of the feedback signal SF after a predetermined time by repeatedly performing the above-described looping operation.
In case where the reference signal is changed or a frequency division ratio of the frequency divider is changed, the PLL repeats the feedback loop procedures in order to obtain a new fixed phase. At this time, a locking time taken to reach a phase-locked state is determined by a characteristic function of the PLL.
Two methods for reducing the locking time are disclosed in Yasuaki Sumi, xe2x80x9cFAST SETTLING PLL FREQUENCY SYNTHESIZER UTILIZING THE FREQUENCY DETECTOR METHOD SPEEDUP CIRCUITxe2x80x9d, IEEE Transaction on Consumer Electronics, Vol. 43, No. 3, August 1997.
One method is to employ a frequency detector method speedup circuit (FDMSC). The FDMSC includes a frequency detector for detecting a frequency difference and a charge controller. The charge controller is used to fix an input signal until a first frequency locking is completed when a frequency division ration is changed.
The other method is to add an LPF, which has a changeable-bandwidth, to the FDMSC. In this method, a resistance ratio that determines a gain of an active LPF is adjusted according to a frequency difference. At this time, since the LPF has a smaller time constant only at a rising time, an input voltage signal of the VCO can reach fast a target voltage, thereby reducing the locking time.
In these methods, however, there are problems that a circuit configuration becomes complicated and a chip size is increased, thereby causing an increase in the power dissipation of the PLL.
It is, therefore, an object of the present invention to provide a phase-locked loop (PLL) which is capable of obtaining a fast locking time and a reduced jitter.
In accordance with an aspect of the present invention, there is provided a phase/frequency detector for comparing a phase/frequency of a reference signal having a reference frequency and that of a feedback signal having a feedback frequency in a phase locked loop (PLL), comprising: a NAND gate logic circuit for NANDing a first signal first signal and a second signal to output a NANDed signal; a first latch means for latching the NANDed signal and outputting the first signal in response to the reference signal; and a second latch means for latching the NANDed signal and outputting the second signal in response to the feedback signal.
In accordance with another aspect of the present invention, there is provided a phase locked loop (PLL) comprising: a phase/frequency detection means for comparing a phase/frequency of a reference signal having a predetermined reference frequency with that of a feedback signal having a predetermined feedback frequency to generate a up pulse and a down pulse according to a phase/frequency difference, wherein the phase/frequency detection means includes two latch circuits and one gate logic circuit; a charge pump means for providing a positive pump current signal and a negative pump current signal in response to the up pulse and the down pulse;
a filter means for converting the positive pump current signal and the negative pump current signal into corresponding voltage signal; and a voltage controlled oscillation means for receiving the voltage signal to generate an output signal having a predetermined oscillation frequency.
Furthermore, the phase-locked loop (PLL) further comprises a filter control means for performing a switching operation in response to the up pulse and the down pulse, thereby changing a resistance of the filter means.